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lt1683 1 1683fd typical application description slew rate controlled ultralow noise push-pull dc/dc controller the lt ? 1683 is a switching regulator controller designed to lower conducted and radiated electromagnetic interference (emi). ultralow noise and emi are achieved by controlling the voltage and current slew rates of external n-channel mosfet switches. current and voltage slew rates can be independently set to optimize harmonic content of the switching waveforms vs effciency. the lt1683 can reduce high frequency harmonic power by as much as 40db with only minor losses in effciency. the lt1683 utilizes a dual output (push-pull) current mode architecture optimized for low noise topologies. the ic includes gate drivers and all necessary oscillator, control and protection circuitry. unique error amp circuitry can regulate both positive and negative voltages. the oscil - lator may be synchronized to an external clock for more accurate placement of switching harmonics. protection features include gate drive lockout for low v in , opposite gate lockout, soft-start, output current limit, short-circuit current limiting, gate drive overvoltage clamp and input supply undervoltage lockout. ultralow noise 48v to 5v dc/dc converter features applications n greatly reduced conducted and radiated emi n low switching harmonic content n independent control of output switch voltage and current slew rates n greatly reduced need for external filters n dual n-channel mosfet drivers n 20khz to 250khz oscillator frequency n easily synchronized to external clock n regulates positive and negative voltages n easier layout than with conventional switchers n power supplies for noise sensitive communication equipment n emi compliant offine power supplies n precision instrumentation systems n isolated supplies for industrial automation n medical instruments n data acquisition systems a b mbrs340 midcom 31244 22h 150f os-con mbrs340 mbr0530 22h optional 2100f poscap 5v/2a 3 10 1683 ta01 11 13 shdn cap a nfb lt1683 gnd v in 17 14 2 gcl ss v5 sync gate a 5 1 c t cap b 6 18 r t gate b 7 19 8 r csl 16 v c 15 12 r vsl cs 4 pgnd 20 fb 9 5pf 5pf si9422 si9422 0.1 976 23.2k 10nf 1.5k 3.3k 25k 25k 3.3k 16.9k 1.2nf 39f 63v 48v 68f 20v 11v 8.2v 51k 510 0.5w 2n3904 1n4148 10f 20v 30pf 22nf 0.22f 7.50k 2.49k fzt853 10pf 200v 30pf 10pf 200v 5v output noise (bandwidth = 100mhz) a 200v/div b 20mv/div 200v p-p 5s/div 1683 ta01a l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and directsense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
lt1683 2 1683fd pin configuration absolute maximum ratings supply voltage (v in ) ................................................. 20v gate drive current ..................................... internal limit v5 current .................................................. internal limit shdn pin voltage ..................................................... 20v feedback pin voltage (trans. 10ms) ...................... 10v feedback pin current ............................................ 10ma negative feedback pin voltage (trans. 10ms) ......... 10v cs pin ........................................................................... 5v gcl pin ....................................................................... 16v ss pin ........................................................................... 3v operating junction temperature range (note 3) .................................................. C 40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 5 6 7 8 9 10 top view g package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 gate a cap a gcl cs v5 sync c t r t fb nfb pgnd gate b cap b v in r vsl r csl shdn ss v c gnd t jmax = 150c, ja = 110c/ w electrical characteristics symbol parameter conditions min typ max units error amplifers v ref reference voltage measured at feedback pin l 1.235 1.250 1.265 v i fb feedback input current v fb = v ref l 250 1000 na fb reg reference voltage line regulation 2.7v v in 20v l 0.012 0.03 %/v v nfr negative feedback reference voltage measured at negative feedback pin with feedback pin open l C 2.56 C 2.500 C 2.45 v i nfr negative feedback input current v nfb = v nfr C 37 C 25 a nfb reg negative feedback reference voltage line regulation 2.7v v in 20v l 0.009 0.03 %/v g m error amplifer transconductance ?i c = 50a l 1100 700 1500 2200 2500 mho mho the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v c = 0.9v, v fb = v ref , r vsl , r csl = 16.9k, r t = 16.9k and other pins open unless otherwise noted. order information lead free finish tape and reel part marking* package description temperature range lt1683eg#pbf lt1683eg#trpbf 1683 20-lead plastic ssop C 40c to 125c lt1683ig#pbf lt1683ig#trpbf 1683 20-lead plastic ssop C 40c to 125c lead based finish tape and reel part marking* package description temperature range lt1683eg lt1683eg#tr 1683 20-lead plastic ssop C 40c to 125c lt1683ig lt1683ig#tr 1683 20-lead plastic ssop C 40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
lt1683 3 1683fd symbol parameter conditions min typ max units i esk error amp sink current v fb = v ref + 150mv, v c = 0.9v l 120 200 350 a i esrc error amp source current v fb = v ref C 150mv, v c = 0.9v l 120 200 350 a v clh error amp clamp voltage high clamp, v fb = 1v 1.27 v v cll error amp clamp voltage low clamp, v fb = 1.5v 0.12 v a v error amplifer voltage gain 180 250 v/v fb ov fb overvoltage shutdown outputs drivers disabled 1.47 v i ss soft-start charge current v ss = 1v 9.0 12 a oscillator and sync f max max switch frequency 250 khz f sync synchronization frequency range oscillator frequency = 250khz 290 khz v sync sync pin input threshold l 0.7 1.4 2.0 r sync sync pin input resistance 40 k gate drives (specifcations apply to either a or b unless otherwise noted) dc max maximum switch duty cycle r vsl = r csl = 4.85k, osc frequency = 25khz l 45 46 % vg on gate on voltage v in = 12, gcl = 12 v in = 12, gcl = 8 10 7.6 10.4 7.9 10.7 8.1 v v vg off gate off voltage v in = 12v 0.2 0.35 v ig so max gate source current v in = 12v 0.3 a ig sk max gate sink current v in = 12v 0.3 a v inuvlo gate drive undervoltage lockout (note 5) v gcl = 6.5v, gates enabled 7.3 7.5 v current sense t ibl switch current limit blanking time 100 ns v sense sense voltage shutdown voltage v c pulled low l 86 103 120 mv v sensef sense voltage fault threshold l 230 300 mv slew control (for the following slew tests see test circuit in figure 1b) v slewr output voltage slew rising edge r vsl = r csl = 17k 26 v/s v slewf output voltage slew falling edge r vsl = r csl = 17k 19 v/s vi slewr output current slew rising edge (cs pin voltage) r vsl = r csl = 17k 0.21 v/s vi slewf output current slew falling edge (cs pin voltage) r vsl = r csl = 17k 0.21 v/s supply and protection v inmin minimum input voltage (note 4) v gcl = v in l 2.55 3.6 v i vin supply current (note 2) r vsl = r csl = 17k , v in = 12 r vsl = r csl = 17k , v in = 20 l l 25 35 45 55 ma ma v shdn shutdown turn-on threshold l 1.31 1.39 1.48 v ?v shdn shutdown turn-on voltage hysteresis l 50 110 180 mv i shdn shutdown input current hysteresis l 10 24 35 a v5 5v reference voltage 6.5v v in 20v, iv5 = 5ma 6.5v v in 20v, iv5 = C 5ma 4.85 4.80 5 5 5.20 5.15 v v iv5 sc 5v reference short-circuit current v in = 6.5v source v in = 6.5v sink 10 C10 ma ma electrical characteristics the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v c = 0.9v, v fb = v ref , r vsl , r csl = 16.9k, r t = 16.9k and other pins open unless otherwise noted.
lt1683 4 1683fd feedback voltage and input current vs temperature negative feedback voltage and input current vs temperature feedback overvoltage shutdown vs temperature error amp transconductance vs temperature error amp output current vs feedback pin voltage from nominal electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: supply current specifcation includes loads on each gate as in figure 1a. actual supply currents vary with operating frequency, operating voltages, v5 load, slew rates and type of external fet. note 3: the lt1683e is guaranteed to meet performance specifcations from 0c to 70c. specifcations over the C40c to 125c operating range are assured by design, characterization and correlation with statistical process controls. the lt1683i is guaranteed and tested over the C 40 to 125 operating temperature range. note 4: output gate drivers will be enabled at this voltage. the gcl voltage will also determine drivers activity. note 5: gate drivers are ensured to be on when v in is greater than the maximum value. typical performance characteristics temperature (c) ?50 ?25 0 25 50 75 100 125 150 feedback voltage (v) 1683 g01 1.260 1.258 1.256 1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240 fb input current (na) 750 700 650 600 550 500 450 400 350 300 250 temperature (c) ?50 ?25 0 25 50 75 100 125 150 negative feedback voltage (v) 1683 g02 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 nfb input current (a) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 temperature (c) ?50 ?25 0 25 50 75 100 125 150 feedback voltage (v) 1683 g03 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 temperature (c) ?50 ?25 0 25 50 75 100 125 150 transconductance (mho) 1683 g04 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 feedback pin voltage from nominal (mv) ?400 ?300 ?200 ?100 0 100 200 300 400 current (a) 1683 g05 500 400 300 200 100 0 ?100 ?200 ?300 ? 400 ? 500 ? 40c 125c 25c
lt1683 5 1683fd typical performance characteristics v in current vs temperature cs pin to v c pin transfer function slope compensation gate drive a/b high voltage vs temperature gate drive a/b low voltage vs temperature cs pin trip and cs fault voltage vs temperature shdn pin on and off thresholds vs temperature shdn pin hysteresis current vs temperature v c pin threshold and clamp voltage vs temperature temperature (c) ?50 ?25 0 25 50 75 100 125 150 v c pin voltage (v) 1683 g06 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 temperature (c) ?50 ?25 0 25 50 75 100 125 150 cs pin voltage (mv) 1683 g07 240 220 200 180 160 140 120 100 80 fault trip temperature (c) ?50 ?25 0 25 50 75 100 125 150 shdn pin voltage (v) 1683 g08 1.50 1.45 1.40 1.35 1.30 1.25 on off temperature (c) ?50 ?25 0 25 50 75 100 125 150 shdn pin current (a) 1683 g09 27 25 23 21 19 17 15 temperature (c) ?50 ?25 0 25 50 75 100 125 150 v in current (ma) 1683 g10 24 22 20 18 16 14 12 10 v in = 12 r csl , r vsl = 5.7k with no external mosfets v in = 20 r csl , r vsl = 17k v in = 12 r csl , r vsl = 17k cs pin voltage (mv) 0 20 40 60 80 100 120 v c pin voltage (v) 1683 g11 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 t a = 25c duty cycle (%) 0 10 20 30 40 50 percent of max cs voltage 1683 g12 110 100 90 80 70 60 50 v c pin = 0.9v t a = 25c temperature (c) ?50 ?25 0 25 50 75 100 125 150 gate drive a/b pin voltage (v) 1683 g13 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 9.90 9.80 9.70 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 gcl = 12v gcl = 6v v in = 12v no load temperature (c) ?50 ?25 0 25 50 75 100 125 150 gate drive a/b pin voltage (v) 1683 g14 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 v in = 12v no load
lt1683 6 1683fd typical performance characteristics soft-start current vs temperature v5 voltage vs load current gate drive undervoltage lockout voltage vs temperature temperature (c) ?50 ?25 0 25 50 75 100 125 150 v in pin voltage (v) 1683 g15 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 gcl = 6v temperature (c) ?50 ?25 0 25 50 75 100 125 150 ss pin current (a) 1683 g16 9.5 9.3 9.1 8.9 8.7 8.5 8.3 8.1 7.9 7.7 7.5 ss voltage = 0.9v load current (ma) ?15 ?10 ?5 0 5 10 15 v5 pin voltage (v) 1683 g17 5.08 5.06 5.04 5.02 5.00 4.98 4.96 t = 125c t = 25c t = ? 40c pin functions part supply v5 (pin 5): this pin provides a 5v output that can sink or source 10ma for use by external components. v5 source current comes from v in . sink current goes to gnd. v in must be greater than 6.5v in order for this voltage to be in regulation. if this pin is used, a small capacitor (<1f) may be placed on this pin to reduce noise. this pin can be left open if not used. gnd (pin 11): signal ground. the internal error ampli - fer, negative feedback amplifer, oscillator, slew control circuitry, v5 regulator, current sense and the bandgap reference are referred to this ground. keep the connec - tion to this pin, the feedback divider and v c compensation network free of large ground currents. shdn (pin 14): the shutdown pin can disable the switcher. grounding this pin will disable all internal circuitry. increasing shdn voltage will initially turn on the internal bandgap regulator. this provides a precision threshold for the turn on of the rest of the ic. as shdn increases past 1.39v the internal ldo regulator turns on, enabling the control and logic circuitry. 24a of current is sourced out of the pin above the turn on threshold. this can be used to provide hysteresis for the shutdown function. the hysteresis voltage will be set by the thevenin resistance of the resistor divider driving this pin times the current sourced out. above approximately 2.1v the hysteresis current is removed. there is approximately 0.1v of voltage hysteresis on this pin as well. the pin can be tied high (to v in for instance). v in (pin 17): input supply. all supply current for the part comes from this pin including gate drives and v5 regula - tor. charge current for gate drives can produce current pulses of hundreds of milliamperes. bypass this pin with a low esr capacitor. when v in is below 2.55v the part will go into supply undervoltage lockout where the gate drivers are driven low. this, along with gate drive undervoltage lockout, prevents unpredictable behavior during power up. pgnd (pin 20): power driver ground. this ground comes from the mosfet gate drivers. this pin can have several hundred milliamperes of current on it when the external mosfets are being turned off. oscillator sync (pin 6): the sync pin can be used to synchronize the part to an external clock. the oscillator frequency
lt1683 7 1683fd pin functions should be set close to the external clock frequency. syn - chronizing the clock to an external reference is useful for creating more stable positioning of the switcher voltage and current harmonics. this pin can be left open or tied to ground if not used. c t (pin 7): the oscillator capacitor pin is used in conjunc - tion with r t to set the oscillator frequency. for r t = 16.9k: c osc (nf) = 129/f osc (khz) r t (pin 8): the oscillator resistor pin is used to set the charge and discharge currents of the oscillator capacitor. the nominal value is 16.9k. it is possible to adjust this re - sistance 25% to set oscillator frequency more accurately. gate drive gate a, gate b (pins 1, 19): these pins connect to the gates of the external n-channel mosfets. gate a and gate b turn on with alternate clock cycles. these drivers are capable of sinking and sourcing at least 300ma. the gcl pin sets the upper voltage of the gate drive. the gate pins will not be activated until v in reaches a minimum voltage as defned by the gcl pin (gate undervoltage lockout). the gate drive outputs have current limit protection to safe guard against accidental shorts. if the gate drive voltage is greater than about 1v the opposite gate drive is inhibited thus preventing cross conduction. gcl (pin 3): this pin sets the maximum gate voltage to the gate a and gate b pins to the mosfet gate drives. this pin should be either tied to a zener, a voltage source or v in . if the pin is tied to a zener or a voltage source, the maximum gate drive voltage will be approximately v gcl C 0.2v. if it is tied to v in , the maximum gate voltage is approximately v in C 1.6. approximately 50a of current can be sourced from this pin if v gcl < v in C 0.8v. this pin also controls undervoltage lockout of the gate drives. if the pin is tied to a zener or voltage source, the gate drive will not be enabled until v in > v gcl + 0.8v. if this pin is tied to v in , then undervoltage lockout is disabled. there is an internal 19v zener tied from this pin to ground to provide a fail-safe for maximum gate voltage. slew control cap a, cap b (pins 2, 18): these pins are the feedback nodes for the external voltage slewing capacitors. normally a small 1pf to 5pf capacitor is connected from this pin to the drain of its respective mosfet. the voltage slew rate is inversely proportional to this capacitance and proportional to the current that the part will sink and source on this pin. that current is inversely proportional to r vsl . r csl (pin 15): a resistor to ground sets the current slew rate for the external drive mosfets during switching. the minimum resistor value is 3.3k and the maximum value is 68k. the time to slew between on and off states of the mosfet current will determine how the di/dt related harmonics are reduced. this time is proportional to r csl and r s (the current sense resistor) and maximum cur - rent. longer times produce a greater reduction of higher frequency harmonics. r vsl (pin 16): a resistor to ground sets the voltage slew rate for the drains of the external drive mosfets. the minimum resistor value is 3.3k and the maximum value is 68k. the time to slew between on and off states on the mosfet drain voltage will determine how harmonics are reduced from this source. this time is proportional to r vsl , c va/b and the input voltage. longer times produce more rolloff of harmonics. c va/b is the equivalent capacitance from cap a or b to the drain of the mosfet. switch mode control cs (pin 4): this is the input to the current sense amplifer. it is used for both current mode control and current slewing of the external mosfets. current sense is accomplished via a sense resistor (r s ) connected from the sources of the external mosfets to ground. cs is connected to the top of r s . current sense is referenced to the gnd pin.
lt1683 8 1683fd pin functions the switch maximum operating current will be equal to 0.1v/r s . at cs = 0.1v, the gate drivers will be immediately turned off (no slew control). if cs = 0.22v in addition to the drivers being turned off, v c and ss will be discharged to ground (short-circuit protec - tion). this will hasten turn off on subsequent cycles. fb (pin 9): the feedback pin is used for positive voltage sensing. it is the inverting input to the error amplifer. the noninverting input of this amplifer connects internally to a 1.25v reference. if the voltage on this pin exceeds the reference by 220mv, then the output drivers will immediately turn off the exter - nal mosfets (no slew control). this provides for output overvoltage protection when this input is below 0.9v then the current sense blanking will be disabled. this will assist start up. nfb (pin 10): the negative feedback pin is used for sens- ing a negative output voltage. the pin is connected to the inverting input of the negative feedback amplifer through a 100k source resistor. the negative feedback amplifer provides a gain of C 0.5 to the fb pin. the nominal regula - tion point would be C 2.5v on nfb. this pin should be left open if not used. if nfb is being used then overvoltage protection will occur at 0.44v below the nfb regulation point. at nfb < C1.8 current sense blanking will be disabled. v c (pin 12): the compensation pin is used for frequency compensation and current limiting. it is the output of the error amplifer and the input of the current comparator. loop frequency compensation can be performed with an rc network connected from the v c pin to ground. the voltage on v c is proportional to the switch peak current. the normal range of voltage on this pin is 0.25v to 1.27v. however, during slope compensation the upper clamp voltage is allowed to increase with the compensation. during a short-circuit fault the v c pin will be discharged to ground. ss (pin 13): the ss pin allows for ramping of the switch current threshold at startup. normally a capacitor is placed on this pin to ground. an internal 9a current source will charge this capacitor up. the voltage on the v c pin cannot exceed the voltage on ss. thus peak current will ramp up as the ss pin ramps up. during a short circuit fault the ss pin will be discharged to ground thus reinitializing soft-start. when ss is below the v c clamp voltage the v c pin will closely track the ss pin. this pin can be left open if not used. test circuits + ? 5pf in5819 20ma 2 1683 f01a zvn3306a 10 gate a/gate b cap a/cap b figure 1a. typical test circuitry figure 1b. test circuit for slew + ? 5pf in5819 0.9a 0.1 1683 f01b si4450dy 10 gate a/gate b cs cap a/cap b
lt1683 9 1683fd block diagram + v c nfb fb 1683 bd ss c ss slew control v reg v in v in c in v5 to drivers t qb q ff s q ff r oscillator ? + negative feedback amp + ? ? + error amp 1.25v 100k 50k comp ? + sense amp shdn r vsl r csl r csl regulator c vc r t c t c t r t r vsl cap a cap b gate a ma g cl gate b pgnd cs mb c va c vb r sense sync gnd sub
lt1683 10 1683fd operation in noise sensitive applications switching regulators tend to be ruled out as a power supply option due to their pro - pensity for generating unwanted noise. when switching supplies are required due to effciency or input/output constraints, great pains must be taken to work around the noise generated by a typical supply. these steps may include pre and post regulator fltering, precise synchroni - zation of the power supply oscillator to an external clock, synchronizing the rest of the circuit to the power supply oscillator or halting power supply switching during noise sensitive operations. the lt1683 greatly simplifes the task of eliminating supply noise by enabling the design of an inherently low noise switching regulator power supply. the lt1683 is a fxed frequency, current mode switching regulator with unique circuitry to control the voltage and current slew rates of the output switches. current mode control provides excellent ac and dc line regulation and simplifes loop compensation. slew control capability provides much greater control over the power supply components that can create conducted and radiated electromagnetic interference. compliance with emi standards will be an easier task and will require fewer external fltering components. the lt1683 uses two external n-channel mosfets as the power switches. this allows the user to tailor the drive conditions to a wide range of voltages and currents. current mode control referring to the block diagram. a switching cycle begins with an oscillator discharge pulse, which resets the rs fip-fop, turning on one of the external mosfet drivers. the switch current is sensed across the external sense resistor and the resulting voltage is amplifed and com - pared to the output of the error amplifer (v c pin). the driver is turned off once the output of the current sense amplifer exceeds the voltage on the v c pin. in this way pulse by pulse current limit is achieved. the toggle fip-fop ensures that the two mosfets are enabled on alternate clock cycles. internal slope compensation is provided to ensure stability under high duty cycle conditions. output regulation is obtained using the error amp to set the switch current trip point. the error amp is a transconductance amplifer that integrates the difference between the feedback output voltage and an internal 1.25v reference. the output of the error amp adjusts the switch current trip point to provide the required load current at the desired regulated output voltage. this method of controlling current rather than voltage provides faster input transient response, cycle-by-cycle current limiting for better output switch protection and greater ease in compensating the feedback loop. the v c pin is used for loop compensation and current limit adjustment. during normal operation the v c voltage will be between 0.25v and 1.27v. an external clamp on v c or ss may be used for lowering the current limit. the negative voltage feedback amplifer allows for direct regulation of negative output voltages. the voltage on the nfb pin gets amplifed by a gain of C 0.5 and driven on to the fb input, i.e., the nfb pin regulates to C2.5v while the amplifer output internally drives the fb pin to 1.25v as in normal operation. the negative feedback amplifer input impedance is 100k (typ) referred to ground. soft-start control of the switch current during start-up can be obtained by using the ss pin. an external capacitor from ss to ground is charged by an internal 9a current source. the voltage on v c cannot exceed the voltage on ss. thus as the ss pin ramps up the v c voltage will be allowed to ramp up. this will then provide for a smooth increase in switch maximum current. ss will be discharged as a result of the cs voltage exceeding the short-circuit threshold of approximately 0.22v. slew control control of output voltage and current slew rates is achieved via two feedback loops. one loop controls the mosfet drain dv/dt and the other loop controls the mosfet di/dt. the voltage slew rate uses an external capacitor between cap a or cap b and the respective mosfet drain. these integrating caps close the voltage feedback loop. the external resistor, r vsl , sets the current for the integrator.
lt1683 11 1683fd the voltage slew rate is thus inversely proportional to both the value of capacitor and r vsl . the current slew feedback loop consists of the voltage across the external sense resistor, which is internally ampli - fed and differentiated. the derivative is limited to a value set by r csl . the current slew rate is thus inversely proportional to both the value of sense resistor and r csl. the two control loops are combined internally so that a smooth transition from current slew control to voltage slew control is obtained. when turning on, the driver cur - rent will slew before voltage. when turning off, voltage will slew before current. in general it is desirable to have r vsl and r csl of similar value. internal regulator most of the control circuitry operates from an internal 2.4v low dropout regulator that is powered from v in . the internal low dropout design allows v in to vary from 2.7v to 20v with stable operation of the controller. when shdn < 1.3v the internal regulator is completely disabled. 5v regulator a 5v regulator is provided for powering external circuitry. this regulator draws current from v in and requires v in to be greater than 6.5v to be in regulation. it can sink or source 10ma. the output is current limited to prevent against destruction from accidental short circuits. safety and protection features there are several safety and protection features on the chip. the frst is overcurrent limit. normally the gate drivers will go low when the output of the internal sense amplifer exceeds the voltage on the v c pin. the v c pin is clamped such that maximum output current is attained when the cs pin voltage is 0.1v. at that level the outputs will be immediately turned off (no slew). the effect of this control is that the output voltage will foldback with overcurrent. in addition, if the cs voltage exceeds 0.22v, the v c and ss pins will be discharged to ground also, resetting the soft-start function. thus if a short is present this will allow for faster mosfet turnoff and less mosfet stress. if the voltage on the fb pin exceeds regulation by ap - proximately 0.22v, the outputs will immediately go low. the implication is that there is an overvoltage fault. the voltage on gcl determines two features. the frst is the maximum gate drive voltage. this will protect the mosfet gate from overvoltage. with gcl tied to a zener or an external voltage source then the maximum gate driver voltage is approximately v gcl C 0.2v. if gcl is tied to v in , then the maximum gate voltage is determined by v in and is approximately v in C 1.6v. there is an internal 19v zener on the gcl pin that prevents the gate driver pin from exceeding ap- proximately 19v. in addition, the gcl voltage determines undervoltage lockout of the gate drives. this feature disables the gate drivers if v in is too low to provide adequate voltage to turn on the mosfets. this is helpful during start-up to ensure the mosfets have suffcient gate drive to saturate. if gcl is tied to a voltage source or zener less than 6.8v, the gate drivers will not turn on until v in exceeds gcl voltage by 0.8v. for v gcl above 6.5v, the gate drives are ensured to be off for v in < 7.3v and they will be turned on by v gcl + 0.8v. if gcl is tied to v in , the gate drivers are always enabled (undervoltage lockout is disabled). when driving a push-pull transformer, it is important to make sure that both drivers are not on at the same time. even though runaway cannot occur under such cross conduction with this chip because current slew is regu - lated, increased current would be possible. this chip has opposite gate lockout whereby when one mosfet is on the other mosfet cannot be turned on until the gate of the frst drops below 1v. this ensures that cross conduc - tion will not occur. the gate drives have current limits for the drive currents. if the sink or source current is greater than 300ma then the current will be limited. the v5 regulator also has internal current limiting that will only guarantee 10ma output current . operation
lt1683 12 1683fd operation there is also an on-chip thermal shutdown circuit that will turn off the outputs in the event the chip temperature rises to dangerous levels. thermal shutdown has hysteresis that will cause a low frequency (<1khz) oscillation to occur as the chip heats up and cools down. the chip has an undervoltage lockout feature that will force the gate drivers low in the event that v in drops below 2.5v. this ensures predictable behavior during start-up and shutdown. shdn can be used in conjuction with an external resistor divider to completely disable the part if the input voltage is too low. this can be used to ensure adequate voltage to reliably run the converter. see the section in applications information. table 1 summarizes these features. table 1. safety and protection features feature function effect on gate drivers slew control effect on vc, ss maximum current fault turn off fets at maximum switch current (v sense = 0.1) immediately goes low overridden none short-circuit fault turn off fets and reset v c for short-circuit (v sense = 0.2) immediately goes low overridden discharge v c , ss to gnd overvoltage fault turn off drivers if fb > v reg + 0.22v (output overvoltage) immediately goes low overridden none gcl clamp set max gate voltage to prevent fet gate breakdown limits max voltage none none gate drive undervoltage lockout disable gate drives when v in is too low. set via gcl pin immediately goes low overridden none thermal shutdown turn off drivers if chip temperature is too hot immediately goes low overridden none opposite gate lockout prevents opposite driver from turning on until driver is off (cross conduction in transformer) inhibits turn on of opposite driver none none v in undervoltage lockout disable part when v in ? 2.55v immediately goes low overridden none gate drive source and sink current limit limit gate drive current limit drive current none none v5 source/sink current limit limit current from v5 none none none shutdown disable part when shdn <1.3v
lt1683 13 1683fd reducing emi from switching power supplies has tradition - ally invoked fear in designers. many switchers are designed solely on effciency and as such produce waveforms flled with high frequency harmonics that then propagate through the rest of the system. the lt1683 provides control over two of the more impor - tant variables for controlling emi with switching inductive loads: switch voltage slew rate and switch current slew rate. the use of this part will reduce noise and emi over conventional switch mode controllers. because these variables are under control, a supply built with this part will exhibit far less tendency to create emi and less chance of encountering problems during production. it is beyond the scope of this data sheet to get into emi fundamentals. application note 70 contains much informa - tion concerning noise in switching regulators and should be consulted. oscillator frequency the oscillator determines the switching frequency and therefore the fundamental positioning of all harmonics. the use of good quality external components is important to ensure oscillator frequency stability. the oscillator is of a sawtooth design. a current defned by external resistor, r t , is used to charge and discharge the capacitor, c t . the discharge rate is approximately ten times the charge rate. by allowing the user to have control over both compo - nents, trimming of oscillator frequency can be more easily achieved. the external capacitance c t is chosen by: c t (nf) = 2180 f(khz) ? r t (k ? ) where f is the desired oscillator frequency in khz. for r t equal to 16.9k, this simplifes to: c t (nf) = 129 f(khz) e.g., c t = 1.29nf for f = 100khz applications information nominally r t should be 16.9k. since it sets up current, its temperature coeffcient should be selected to compliment the capacitor. ideally, both should have low temperature coeffcients. oscillator frequency is important for noise reduction in two ways. first the lower the oscillator frequency the lower the waveforms harmonics, making it easier to flter them. second the oscillator will control the placement of the output voltage harmonics which can aid in specifc problems where you might be trying to avoid a certain frequency bandwidth. oscillator sync if a more precise frequency is desired (e.g., to accurately place harmonics) the oscillator can be synchronized to an external clock. set the rc timing components for an oscillator frequency 10% lower than the desired sync frequency. drive the sync pin with a square wave (with greater than 1.4v amplitude). the rising edge of the sync square wave will initiate clock discharge. the sync pulse should have a minimum pulse width of 0.5s. be careful in syncing to frequencies much different from the part since the internal oscillator charge slope determines slope compensation. it would be possible to get into subharmonic oscillation if the sync doesnt al - low for the charge cycle of the capacitor to initiate slope compensation. in general, this will not be a problem until the sync frequency is greater than 1.5 times the oscillator free-run frequency. slew rate setting the primary reason to use this part is to gain advantage of lower emi and noise due to slew control. the rolloff in higher frequency harmonics has its theoretical basis with two primary components. first, the clock frequency sets the fundamental positioning of harmonics and second, the associated normal frequency rolloff of harmonics.
lt1683 14 1683fd applications information this part creates a second higher frequency rolloff of harmonics that inversely depends on the slew time, the time that voltage or current spends between the off state and on state. this time is adjustable through the choice of the slew resistors, the external resistors to ground on the r vsl and r csl pins and the external components used for the external voltage feedback capacitors c av , c bv (from cap a or cap b to their respective mosfet drains) and the sense resistor. lower slew rates (longer slew times, lower frequency for harmonics rolloff) is created with higher values of r vsl , r csl , c av , c bv and the current sense resistor. setting the voltage and current slew rates should be done empirically. the most practical way of determining these components is to set c av , c bv and the sense resistor value. then, start by making r vsl , r csl each a 50k resistor pot in series with 3.3k. starting from the lowest resistor set - ting (fast slew) adjust the pots until the noise level meets your guidelines. note that slower slewing waveforms will dissipate more power so that effciency will drop. you can monitor this as you make your slew adjustment by measuring input and output voltage and their respective currents. monitor the mosfet temperature as slew rates are slowed. these components will heat up as effciency decreases. measuring noise should be done carefully. it is easy to introduce noise by poor measurement techniques. consult an70 for recommended measurement techniques. keeping probe ground leads very short is essential. usually it will be desirable to keep the voltage and cur - rent slew resistors approximately the same. there are circumstances where a better optimization can be found by adjusting each separately, but as these values are separated further, a loss of independence of control may occur. it is possible to use a single slew setting resistor. in this case the r vsl and r csl pins are tied together. a resistor with a value of 1.8k to 34k (one-half the individual resis - tors) can then be tied from these pins to ground. in general only the r csl value will be available for adjust - ment of current slew. the current slew time does also depend on the current sense resistor but this resistor is normally set with consideration of the maximum current in the mosfets. setting the voltage slew also involves selection of the capacitors c av , c bv . the voltage slew time is proportional to the output voltage swing (basically input voltage), the external voltage feedback capacitor and the r vsl value. thus at higher input voltages smaller capacitors will be used with lower r vsl values. for a starting point use table 2. table 2 input voltage capacitor value <25v 5pf 50v 2.5pf 100v 1pf smaller value capacitors can be made in two ways. the frst is simply combining two capacitors in series. the equivalent capacitance is then (c1 ? c2)/(c1 + c2). the second method makes use of a capacitor divider. care should be taken that the voltage ratings of the capacitors satisfy the full voltage swing (2x input voltage for push- pull confgurations) thus essentially the same rating as the mosfets. c1 mosfet drain c2 cap a or b c3 1683 f02 figure 2 the equivalent slew capacitance for figure 2 is (c1 ? c2)/(c1 + c2 + c3). positive output voltage setting sensing of a positive output voltage is usually done us - ing a resistor divider from the output to the fb pin. the positive input to the error amp is connected internally to a 1.25v bandgap reference. the fb pin will regulate to this voltage. referring to figure 3, r1 is determined by: r1 = r2 v out 1.25 ? 1 ? ? ? ? ? ?
lt1683 15 1683fd applications information the fb bias current represents a small error and can usually be ignored for values of r1||r2 up to 10k. one word of caution, sometimes a feedback zero is added to the control loop by placing a capacitor across r1. if the feedback capacitively pulls the fb pin above the in - ternal regulator voltage (2.4v), output regulation may be disrupted. a series resistance with the feedback pin can eliminate this potential problem. there is an internal clamp on fb that clamps at 0.7v above the regulation voltage that should also help prevent this problem. nfb pin i nfb 1683 f04 ?v out r2 r1 fb pin 1683 f03 v out r2 r1 figure 3 figure 4 negative output voltage setting negative output voltage can be sensed using the nfb pin. in this case regulation will occur when the nfb pin is at C2.5v. the nominal input bias current for the nfb is C25a (i nfb ), which needs to be accounted for in setting up the divider. referring to figure 4, r1 is chosen such that: r1 = r2 v out ? 2.5 2.5 + r2 ? 25a ? ? ? ? ? ? a suggested value for r2 is 2.5k. the nfb pin is normally left open if the fb pin is being used. dual polarity output voltage sensing certain applications may beneft from sensing both posi - tive and negative output voltages. when doing this each output voltage resistor divider is individually set as previ- ously described. when both fb and nfb pins are used, the lt1683 will act to prevent either output from going beyond its set output voltage. the highest output (lightest load) will dominate control of the regulator. this technique would prevent either output from going unregulated high at no load. however, this technique will also compromise output load regulation. shutdown if shdn is pulled low, the regulator will turn off. as the shdn pin voltage is increased from ground the internal bandgap regulator will be powered on. this will set a 1.39v threshold for turn-on of the internal regulator that runs most of the control circuitry of the regulator. note after the control circuitry powers on, gate driver activity will depend on the voltage of v in with respect to the voltage on gcl. as the shdn pin enables the internal regulator a 24a current will be sourced from the pin that can provide hysteresis for undervoltage lockout. this hysteresis can be used to prevent part shutdown due to input voltage sag from an initial high current draw. in addition to the current hysteresis, there is also approxi - mately 100mv of voltage hysteresis on the shdn pin. when the shdn pin is greater than 2.2v, the hysteretic current from the part will be reduced to essentially zero. if a resistor divider is used to set the turn-on threshold then the resistors are determined by the following equations: v on = ra + rb rb ? ? ? ? ? ? ? v shdn v hyst = ra ? ? v shdn ra rb + i shdn ? ? ? ? ? ? reworking these equations yields: ra = (v hyst ? v shdn ? v on ? ? v shdn ) (i shdn ? v shdn ) rb = (v hyst ? v shdn ? v on ? ? v shdn ) i shdn ? (v on ? v shdn ) ? ? ? ? v in ra rb shdn
lt1683 16 1683fd applications information so if we wanted to turn on at 20v with 2v of hysteresis: ra = 2v ? 1.39v ? 20v ? 0.1v 24a ? 1.39v = 23.4k rb = 2v ? 1.39v ? 20v ? 0.1v 24a ? (20v ? 1.39v) = 1.75k resistor values could be altered further by adding zeners in the divider string. a resistor in series with shdn pin could further change hysteresis without changing turn-on voltage. frequency compensation loop frequency compensation is accomplished by way of a series rc network on the output of the error amplifer (v c pin). v c pin 1683 f06 r vc 2k c vc 0.01f c vc2 4.7nf figure 6 referring to figure 6, the main pole is formed by capaci - tor c vc and the output impedance of the error amplifer (approximately 400k). the series resistor, r vc , creates a zero which improves loop stability and transient response. a second capacitor, c vc2 , typically one-tenth the size of the main compensation capacitor, is sometimes used to reduce the switching frequency ripple on the v c pin. v c pin ripple is caused by output voltage ripple attenuated by the output divider and multiplied by the error amplifer. without the second capacitor, v c pin ripple is: v cpinripple = 1.25 ? v ripple ? gm ? r vc v out where v ripple = output ripple (v p-p ) gm = error amplifer transconductance r vc = series resistor on v c pin v out = dc output voltage to prevent irregular switching, v c pin ripple should be kept below 50mv p-p . worst-case v c pin ripple occurs at maximum output load current and will also be increased if poor quality (high esr) output capacitors are used. the addition of a 0.0047f capacitor for c vc2 pin reduces switching frequency ripple to only a few millivolts. a low value for r vc will also reduce v c pin ripple, but loop phase margin may be inadequate. setting current limit the sense resistor sets the value for maximum operating current. when the cs pin voltage is 0.1v the gate drivers will immediately go low (no slew control). therefore the sense resistor value should be set to r s = 0.1v/i sw(peak) , where i sw(peak) is the peak current in the mosfets. i sw(peak) will depend on the topology and component values and tolerances. certainly it should be set below the saturation current value for the transformer. if cs pin voltage is 0.22v in addition to the drivers going low, v c and ss will be discharged to ground. this is to provide additional protection in the event of a short cir - cuit. by discharging v c and ss, the mosfet will not be stressed as hard on subsequent cycles since the current trip will be set lower. turn-off of the mosfets will normally be inhibited for about 100ns at the start of every turn on cycle. this is to prevent noise from interfering with normal operation of the controller. this current sense blanking does not prevent the outputs from be turned off in the event of a fault. slewing of the gate voltage effectively provides additional blanking. traces to the sense resistor should be kept short and wide to minimize resistance and inductance. large interwinding capacitance in the transformer or high capacitance on the drain of the mosfets will produce a current pulse through the sense resistor during drain voltage slewing. the magnitude of the pulse is c ? dv/dt where c is the capacitance and dv/dt is the voltage slew rate which is controlled by the part. this pulse will increase the sensed current on switch turn-on and can cause pre - mature mosfet turn-off. if this occurs, the transformer may need a different winding technique (see an39) or alternatively, a blanking circuit can be used. please contact the ltc applications group for support if required.
lt1683 17 1683fd soft-start the soft-start pin is used to provide control of switching current during start-up. the max voltage on the v c pin is approximately the voltage on the ss pin. a current source will linearly charge a capacitor on the ss pin. the v c pin voltage will thus ramp also. the approximate time for the voltage on these pins to ramp is (1.31v/9a) ? c ss or approximately 146ms per f. the soft-start current will be initiated as soon as the part turns on. soft-start will be reinititated after a short-circuit fault. thermal considerations most of the ic power dissipation is derived from the v in pin. the v in current depends on a number of factors in - cluding: oscillator frequency; loads on v5; slew settings; gate charge current. additional power is dissipated if v5 sinks current and during the mosfet gate discharge. the power dissipation in the ic will be the sum of: 1) the rms v in current times v in 2) v5 rms sink current times 5v 3) the gate drives rms discharge current times voltage because of the strong v in component it is advantageous to operate the lt1683 at as low a v in as possible. it is always recommended that package temperature be measured in each application. the part has an internal thermal shutdown to minimize the chance of ic destruction but this should not replace careful thermal design. the thermal shutdown feature does not protect the external mosfets. a separate analysis must be done for those devices to ensure that they are operating within safe limits. once ic power dissipation, p dis , is determined die junction temperature is then computed as: t j = t amb + p dis ? ja where t amb is ambient temperature and ja is the package thermal resistance. for the 20-pin ssop, ja is 100c/w. applications information magnetics design of magnetics is dependent on topology. the fol - lowing details the design of the magnetics for a push-pull converter. in this converter the transformer usually stores little energy. the following equations should be considered as the starting point to building a prototype. the following defnitions will be used: v in = input supply voltage r on = switch-on resistance i sw = maximum switch current v out = desired output voltage i out = output current f = oscillator frequency v f = forward drop of the rectifer duty cycle is the major defning equation for this topology. note that the output l and c basically flter the chopped voltage so duty cycle controls output voltage. n is the turns ratio of the transformer. the turns ratio must be large enough to ensure that the transformer can put out a voltage equal to the output voltage plus the diode under minimum input conditions. note the transformer operates at half the oscillator frequency (f). n = v out + v f 2 ? dc max ( ) v in(min) ? i sw r on + r sense ( ) ? ? ? ? dc max is the maximum duty cycle of each driver with respect to the entire cycle, which consists of two periods (a on and b on). so the effective duty cycle is 2 ? dc max . the controller, in general, determines maximum duty cycle. a 44% maximum duty cycle is a guaranteed value for this part. remember to add suffcient margin in the turns ratio to account for ir drops in the transformer windings, worst- case diode forward drops and switch-on voltage. also at very slow slew rates the effective dc may be reduced.
lt1683 18 1683fd there are a number of ways to choose the inductance value for l. we suggest as a starting point that l be selected such that the converter is continuous at i out(max) /4. if your minimum i out is higher than this or your components can handle higher peak currents then use a higher number. applications information 1:n l pri d2 d1 l c r out r sense v out v in 1683 f07 figure 7. push-pull topology continuous operation occurs when the current in the inductor never goes to zero. discontinuous operation occurs when the inductor current drops to zero before the start of the next cycle and can occur with small inductors and light loads. there is nothing inherently bad about discontinuous operation, however, converter control and operation are somewhat different. the inductor is smaller for discontinuous operation but the peak currents in the switch, the transformer, the diodes, inductor and capacitor will be higher which may produce greater losses. for continuous operation the inductor ripple current must be less than twice the output current. the worst case for this is at maximum input (lowest duty cycle, dc min ) but in the following we will evaluate at nominal input since the i out /4 is somewhat arbitrary. note when both inputs are off, the inductor current splits between both secondary outputs and the diode common goes to 0v. looking at the inductor current during off time, output ripple current is: ? i out = 2 ? i out(min) i out(min) = i out(max) / 4 l = v out(min) + v f ( ) ? 1 ? 2 ? dc ( ) ? i out ? f the inductance of the transformer primary should be such that l, when refected into the primary, dominates the input current. in other words, we want the magnetizing current of the transformer small with respect to the current going through the transformer to l. in general, then, the inductance of the primary should be at least fve times that of l refected to the input. this ensures that most of the power will be passed through the transformer to the load. it also increases the power capability of the converter and reduces the peak currents that the switch will see. l pri = 5 ? l n 2 if the magnetizing current is small, say below 100ma, then a smaller l can be used with a higher percentage of the switch current generated by the magnetizing current. with the value of l set, the ripple in the inductor is: ?i l = v out + v f ( ) ? 1 ? 2 ? dc ( ) l ? f however, the peak inductor current is evaluated at maxi - mum load and maximum input voltage (minimum dc). i l(max) = i out(max) + ?i l(max) 2 the magnetizing ripple current can be shown to be: ?i mag = v out + v f n ? l pri ? f and the peak current in the switch is: i sw(peak) = n ? i l(max) + ?i mag this current should be less than the current limit. worst-case switch ripple is: ?i sw(peak) = n ? ?i l(max) + ?i mag in the push-pull converter the maximum switch voltage will be 2 ? v in . because voltage is slew-controlled, the leakage spikes are small. so, the mosfet should have a maximum rated switch voltage at least 20% higher than 2 ? v in .
lt1683 19 1683fd applications information so, given the turns ratio, primary inductance and cur - rent, the transformer can be designed. the design of the transformer will require analyzing the power losses of the transformer and making necessary adjustments. most transformer companies can assist you with designing an optimal solution. for instance midcom, inc. (1-800- 643-2661). linear technologys application group can also help. as an example say we are designing a 48v 20% to 5v 100khz converter with 2a output and 500ma ripple. then starting with a guess for the on voltage of the mosfet plus sense resistor of 0.5v and v f of 0.5v: n = 5 + 0.5 88% ? 48 ? 80% ? 0.5 ( ) = 1 6.1 for continuous operation at i out(min) = i out(max) /4, inductor ripple (the same as output ripple): ?i l = 2 ? 2a 4 = 1a the duty cycle for nominal input is: dc nom = v out + v f 2 ? n v in(nom) ? i sw ? r on ( ) = 5.5 2 6.1 ? 47.5 = 35.3% then: l = 5 + 0.5 ( ) ? 1 ? 2 ? 35.3% ( ) 1a ? 100khz = 16h off-the-shelf components can be used for this inductor. say we choose a 22h inductor, then ripple current at maximum input (dc = 29.1%) is: ?i l = 5 + 0.5 ( ) ? 1 ? 2 ? 29.1% ( ) 22f ? 100khz = 1.03a the maximum inductor current is: i l(max) = 2a + 1.03a 2 = 2.52a primary inductance should be greater than: l pri = 5 ? 22h ? 6.1 2 = 4.1mh the secondary inductance would then be: 4.1mh/6.1 2 = 110h the magnetizing ripple current is approximately: ?i mag = 5.5 1 6.1 ? 4.1mh ? 100khz = 81ma peak switch current is: i sw(peak) = 1 6.1 ? 2.51a + 81ma = 494ma note that you can discern your magnetizing ripple by looking at the refected inductance ripple and subtracting it from the switch current ripple. ?i mag = ?i sw C n ? i l the max ripple current on the switch is: ?i sw(max) = 1.03a 6.1 + 81ma = 0.25a knowing the peak switch current we can go back and iterate with a more accurate switch-on voltage. we would have to know the r on of the fet. in our case our assumptions of a 0.5v switch-on voltage is valid for r on + r sense < 1. capacitors correct choice of input and output capacitors is very important to low noise switcher performance. push-pull topologies and other low noise topologies will in general have continuous currents, which reduce the requirements
lt1683 20 1683fd applications information for capacitance. however, noise depends more on the esr of the capacitors. in addition lower esr can also improve effciency. input capacitors must also withstand surges that occur during the switching of some types of loads. some solid tan - talum capacitors can fail under these surge conditions. design note 95 offers more information but the following is a brief summary of capacitor types and attributes. aluminum electrolytic: low cost and higher voltage. they can be used in this application but in general you will need higher capacitance to achieve low esr. additional nonelectrolytic capacitors may be required to achieve better performance. specialty polymer aluminum: panasonic has come out with their series cd capacitors. while they are only avail - able for voltages below 16v, they have very low esr and good surge capability. solid tantalum: small size and low impedance. typically the maximum voltage rating is 50v. with large surge cur - rents the capacitor may need to be derated or you need a special type such as avx tps line. os-con: lower impedance than aluminum but only avail - able for 35v or less. form factor may be a problem. ceramic: generally used for high frequency and high voltage bypass. they may resonate with their esl before esr becomes dominant. recent multilayer ceramic (mlc) capacitors provide larger capacitance with low esr. there are continuous improvements being made in ca - pacitors so consult with manufacturers as to your specifc needs. input capacitors the input capacitor should have low esr at high frequen - cies since this will be an important factor concerning how much conducted noise is created. there are two separate requirements for input capacitors. the frst is for supply to the parts v in pin. the v in pin will provide current for the part itself and the gate charge current. the worst component from an ac point is the gate charge current. the actual peak current depends on gate capaci - tance and slew rate, being higher for larger values of each. the total current can be estimated by gate charge and frequency of operation. because of the slewing with this part, gate charge is spread out over a longer time period than with a normal fet driver. this reduces capacitance requirements. typically the current will have spikes of under 100ma located at the gate voltage transitions. this is charge/dis - charge to and from the threshold voltage. most slewing occurs with the gate voltage near threshold. since the parts v in will typically be under 15v many op - tions are available for choice of capacitor. values of input capacitor for just v in requirement will typically be in the 50f range with an esr of under 0.1. in addition to the part supply, decoupling of the supply to the transformer needs to be considered. if this is the same supply as the v in pin then that capacitor will need to be increased. however, often with this part the transformer supply will be a higher voltage and as such a separate capacitor. the transformer decoupling capacitor will see the switch current as ripple. this switch current computation can be used to estimate the capacity for these capacitors: c in = 1 ? v cap ?i sw(max) ? esr ? dc min f where ?v cap is the allowed sag on the input capacitor. esr is the equivalent series resistance for the cap. in general allowed sag will be a few tenths of volts. output filter capacitor the output capacitor is chosen both for capacity and esr. the capacity must supply the load current in the switch- off state. while slew control reduces higher frequency components of the ripple current in the capacitor, the capacitor esr and the magnitude of the output ripple
lt1683 21 1683fd applications information current controls the fundamental component. esr should also be low to reduce capacitor dissipation. the capacitance value can be computed by consideration of desired load ripple, duty cycle and esr. c out = 1 ? v out ?i l(max) ? esr ? dc min f mosfet selection there is a wide variety of mosfets to choose from for this part. the part will work with either normal threshold (3v to 4v) or logic-level threshold devices (1v to 2v). select a voltage rating to ensure under worst-case condi - tions that the mosfet will not break down. next choose an r on suffciently low to meet both the power dissipation capabilities of the mosfet package as well as overall ef- fciency needs of the converter. the lt1683 can handle a large range of gate charges. however at very large charge stability may be affected. the power dissipation in the mosfet depends on several factors. the primary element is i 2 r heating when the device is on. in addition, power is dissipated when the device is slewing. an estimate for power dissipation is: pv i i i vr i i in sr in on = + + ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 4 3 4 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + v i f i r dc sr on ? ? ?? 2 where i is the average current, ?i is the ripple current in the switch, i sr is the current slew rate, v sr is the voltage slew rate, f is the oscillator frequency, dc is the duty cycle and r on is the mosfet on-resistance. setting gcl voltage setting the voltage on the gcl pin depends on what type of mosfet is used and the desired gate drive undervoltage lockout voltage. first determine the maximum gate drive that you require. typically you will want it to be at least 2v greater than the maximum threshold. higher voltages will lower the on resistance and increase effciency. be certain to check the maximum allowed gate voltage. often this is 20v but for some logic threshold mosfets it is only 8v to 10v. v gcl needs to be set approximately 0.2v above the desired max gate threshold. in addition v in needs to be at least 1.6v above the gate voltage. the gcl pin can be tied to v in which will result in a maxi- mum gate voltage of v in C 1.6v. this pin also controls undervoltage lockout of the gate drives. the undervoltage lockout will prevent the mosfets from switching until there is suffcient drive present. if gcl is tied to a voltage source or zener less than 6.8v, the gate drivers will not turn on until v in exceeds the gcl voltage by 0.8v. for v gcl above 6.5v, the gate drives are ensured to be off for v in < 7.3v and they will be turned on by v gcl + 0.8v. if gcl is tied to v in , the gate drivers are always on (undervoltage lockout is disabled). approximately 50a of current can be sourced from this pin if v in > v gcl + 0.8v. this could be used to bias a zener. the gcl pin has an internal 19v zener to ground that will provide a failsafe for maximum gate voltage. as an example say we are using a siliconix si4480dy which has r ds(on) rated at 6v. to get 6v, v gcl needs to be set to 6.2v and v in needs to be at least 7.6v.
lt1683 22 1683fd applications information gate driver considerations in general, the mosfets should be positioned as close to the part as possible to minimize inductance. when the part is active the gate drives will be pulled low to less than 0.2v. when the part is off, the gate drives contain a 40k resistor in series with a diode to ground that will offer passive holdoff protection. if you are using some logic-level mosfets this might not be suffcient. a resistor may be placed from gate to ground, however the value should be reasonably high to minimize dc losses and possible ac issues. the gate drive source current comes from v in . the sink current exits through pgnd. in general the decoupling cap should be placed close to these two pins. switching diodes in general, switching diodes should be schottky diodes. size and breakdown voltage depend on the specifc converter. a lower forward drop will improve converter effciency. no other special requirements are needed. pcb layout considerations as with any switcher careful consideration should be given to pc board layout. because this part reduces high frequency emi the board layout is less critical, however high currents and voltages still produce the need for careful board layout to eliminate poor and erratic performance. basic considerations keep the high current loops physically small in area. the main loops are shown in figure 8: the power switch loops (a and b) and the rectifer loop (c and d). these loops can be kept small by physically keeping the components close to one another. in addition, connection traces should be kept wide to lower resistance and inductances. components should be placed to minimize connecting paths. careful attention to ground connections must also be maintained. without getting into elaborate detail be careful that currents from different high current loops do not get coupled into the ground paths of other loops. using singular points of connection for the grounds is the best way to do this. the two major points of connection are the bottom of the input decoupling cap and the bottom of the output decou - pling cap. typically the sense resistor device pgnd and device gnd will tie to the bottom of the input cap. there are two other loops to pay attention to. the current slew involves a high bandwidth control that goes through the mosfet switch, the sense resistor and into the cs pin of the part and out the gate pin to the mosfet. trace inductance and resistance should be kept low on the gate drive trace. the cs trace should have low inductance. the sense resistor should be physically close to pgnd and the mosfets sources. finally care should be taken with the cap a, cap b pins. the part will tolerate stray capacitance to ground on these pins (<5pf) however stray capacitance to the respective drains should be minimized. this path would provide an alternate capacitive path for the voltage slew. more help an70 contains information about low noise switchers and measurement of noise and should be consulted. an19 and an29 also have general knowledge concerning switching regulators. also, our application department is always ready to lend a helping hand. 1683 f08 1 2 4 3 c in c out a a b cs gate a gate b d c figure 8
lt1683 23 1683fd typical applications ultralow noise 48v to 12v dc/dc converter l1 10h c2 33f 16v, 2 c1 33f 16v, 2 mbr01100 l2 10h 3 10 1683 ta03 11 13 shdn cap a nfb lt1683 gnd v in 17 14 2 gcl ss v5 sync gate a 5 1 c t cap b 6 18 r t gate b 7 19 8 r csl 16 v c 15 12 r vsl cs 4 pgnd 20 fb 9 5pf 5pf si9422 si9422 0.068 976 23.2k 10nf 1k 3.3k 25k 25k 3.3k 16.9k 1200pf 47f 100v 48v c3 10f 25v 12v 8.2v 10k 510 0.5w 2n3904 c4 22f 50v 25pf 22nf 0.22f 8.66k 1k 2.74k 10.0k fzt853 5pf 200v 25pf 5pf 200v ?12v/1a 12v/1a d1 d4 d5 d7 d6 d2 d3 ctx0215542 t1 1 2 3,4 5 6 7 8,9 10 c1, c2:sanyo 16tpc33 c3: murata grm235y5v106z c4: nippon thcr60eie226z d1, d2, d3 in4148 d4, d5, d6, d7 mbrs1100 l1, l2: cooper ds50224 t1: cooper ctx02-15542
lt1683 24 1683fd package description g package 20-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g20 ssop 0204 0.09 ? 0.25 (.0035 ? .010) 0 ? 8 0.55 ? 0.95 (.022 ? .037) 5.00 ? 5.60** (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 1 2 3 4 5 6 7 8 9 10 6.90 ? 7.50* (.272 ? .295 ) 1718 14 13 12 11 1516 1920 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ? 0.38 (.009 ? .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout 1.25 0.12
lt1683 25 1683fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 11/10 updated max switch frequency to 150khz in the electrical characteristics section 3 (revision history begins at rev d)
lt1683 26 1683fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt 1110 rev d ? printed in usa related parts typical application part number description comments lt1533 ultralow noise 1a switching regulator push-pull design for low noise isolated supplies lt1534 ultralow noise 2a switching regulator ultralow noise regulator for boost topologies lt1738 ultralow noise dc/dc controller high current output ultralow noise boost regulator; drives external mosfet lt1777 low noise step-down switching regulator programmable di/dt; internally limited dv/dt lt1425 isolated flyback switching regulator excellent regulation without transformer third winding lt1576 1.5a, 200khz step-down switching regulator constant frequency, 1.21v reference voltage lt176x family low dropout, low noise linear regulator 150ma to 3a, sot-23 to to-220 ltc1922-1/ltc3722 synchronous phase modulated full-bridge controllers adaptive directsense tm zero voltage switching, 50w to kilowatts, synchronous rectifcation lt3439 ultralow noise transformer driver 1a push-pull dc/dc transformer driver mbr2045ct coiltronics vp5-1200 4.7h 330f cap a cap b gate a gate b mbr2045ct 1h optional 5v/5a 2330f poscap 3 10 1683 ta02 11 13 shdn cap a nfb lt1683 gnd v in 17 14 2 gcl ss v5 sync gate a 5 1 c t cap b 6 18 r t gate b 7 19 8 r csl 16 v c 15 12 r vsl cs 4 pgnd 20 fb 9 irf540 irf540 10m 10nf 1k 3.3k25k 3.3k 16.9k 1.5nf 39f 24v 68f 20v 11v 8.2v 6.9k 2n3904 1nf 15nf 7.50k 2.49k 25k 3pf 7 3 6?10 11 1 9 4 8 5 2?12 10pf 3pf 10pf ultralow noise 24v to 5v dc/dc converter

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